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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14583B Dual Schmitt Trigger The MC14583B is a dual Schmitt trigger constructed with complementary P-channel and N-channel MOS devices on a monolithic silicon substrate. Each Schmitt trigger is functionally independent except for a common 3-state input and an internally-connected Exclusive OR output for use in line receiver applications. Trigger levels are adjustable through the positive, negative, and common terminals with the use of external resistors. Applications include the speed-up of a slow waveform edge in interface receivers, level detectors, etc. * * * * Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Single Supply Operation Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range * Resistor Adjustable Trigger Levels MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII Value Unit V V - 0.5 to + 18.0 10 500 - 65 to + 150 260 Vin, Vout Iin, Iout PD Tstg TL Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8-Second Soldering) mA mW ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = - 55 to 125C for all packages. BLOCK DIAGRAM 6 5 7 VDD = PIN 16 VSS = PIN 8 _C _C 9 13 15 APos ANeg ACom Aout Ain Aout Dis Bout Bin Bout BPos BNeg BCom 4 11 14 10 12 * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C LOGIC DIAGRAM POSITIVE A NEGATIVE A 65 7 COMMON A Ain 9 2 4 Aout 3 1 TRUTH TABLE 11 Aout 3-STATE OUTPUT DISABLE 13 14 EXCLUSIVE OR 0 0 0 0 1 1 1 1 Inputs A B 0 0 1 1 0 0 1 1 Outputs 0 0 1 1 1 1 0 0 Dis Aout Aout Bout Bout 0 0 Z 0 Z 1 0 1 0 1 0 0 Z 1 Z 1 0 1 1 0 0 1 0 1 1 1 1 1 Z 0 Z 0 0 0 1 1 Z 1 Z 0 Bin 15 10 Bout 12 Bout 1 COMMON B 23 POSITIVE B2 NEGATIVE B REV 3 1/94 Z = High impedance at output VDD = PIN 16 VSS = PIN 8 (c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 MC14583B 1 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 1.2 - 0.25 - 1.62 - 1.8 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 0.25 0.5 1.0 - 1.0 - 0.2 - 0.5 - 1.5 0.51 1.3 3.4 -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 3.5 0.88 2.25 8.8 0.00001 5.0 0.0005 0.0010 0.0015 -- -- -- -- -- -- -- 0.1 7.5 0.25 0.5 1.0 - 0.7 - 0.14 - 0.35 - 1.1 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 7.5 15 30 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Three-State Leakage Current VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD Adc pF Adc IT IT = (1.33 A/kHz) f + IDD IT = (2.65 A/kHz) f + IDD IT = (3.98 A/kHz) f + IDD Adc ITL 15 -- 0.1 -- 0.0001 0.1 -- 3.0 Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.005. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. PIN ASSIGNMENT BCom BPos BNeg Aout ANeg APos ACom VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Bin DIS Bout Aout Bout Ain MC14583B 2 MOTOROLA CMOS LOGIC DATA IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns Symbol tTLH VDD 5.0 10 15 5.0 10 15 tPLH, tPHL 5.0 10 15 tPLH, tPHL 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.85 0.70 0.70 -- -- -- 650 230 150 1100 380 260 750 280 170 225 90 55 3.30 5.70 8.20 1.70 4.30 6.80 1.70 1.40 1.40 0.1 0.15 0.20 1300 460 300 ns 2200 760 520 ns 1500 560 340 ns 450 180 110 -- -- -- -- -- -- 3.40 2.80 2.80 -- -- -- Vdc Min -- -- -- -- -- -- Typ # 180 90 65 100 50 40 Max 360 180 130 200 100 80 ns Unit ns Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time Ain, Bin to Aout, Bout tPLH, tPHL = (1.7 ns/pF) CL + 565 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 125 ns Ain, Bin to Aout, Bout tPLH, tPHL = (1.7 ns/pF) CL + 1015 ns tPLH, tPHL = (0.66 ns/pF) CL + 347 ns tPLH, tPHL = (0.5 ns/pF) CL + 235 ns Ain, Bin to Exclusive OR tPLH, tPHL = (1.7 ns/pF) CL + 665 ns tPLH, tPHL = (0.66 ns/pF) CL + 257 ns tPLH, tPHL = (0.5 ns/pF) CL + 145 ns 3-State Enable, Disable Delay Time (see figure 5) ton, toff = (1.7 ns/pF) CL + 140 ns ton, toff = (0.66 ns/pF) CL + 57 ns ton, toff = (0.5 ns/pF) CL + 30 ns Positive Threshold Voltage (R1, R2 = 5.0 k) Negative Threshold Voltage (R1, R2 = 5.0 k) Hysteresis Voltage (R1, R2 = 5.0 k) Threshold Voltage Variation, A to B (R1, R2 = 5.0 k) tTHL ns tPLH, tPHL ton, toff VT+ VT- Vdc VH Vdc VT Vdc * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. MOTOROLA CMOS LOGIC DATA MC14583B 3 VDD VDD 1 VSS 2 2 SW2 DIS Bin SW1 Ain Aout Aout Vout Output Source Characteristics Test Value Output Under Test Aout, Bout VGS = - VDD VDS = Vout - VDD Switch Position SW1 SW2 1 2 1 1 2 2 Output Sink Characteristics Test Value VGS = VDD VDS = Vout Switch Position SW1 SW2 2 1 1 2 1 1 Bout Bout VSS IO EXTERNAL POWER SUPPLY Aout, Bout Exclusive OR 1 Figure 1. Typical Output Source and Sink Characteristics Test Circuit VDD 500 F ID 0.01 F CERAMIC PULSE GENERATOR 1 Ain DIS Aout Aout CL CL CL CL CL fout, Ain fout, Bin PULSE GENERATOR 2 Bin Bout Bout VSS Figure 2. Power Dissipation Test Circuit and Waveforms A -- Feedback scheme for independent threshold adjustment: POSITIVE COMMON NEGATIVE R2 TYPICAL THRESHOLD POINT (%VDD) R1 80 70 60 50 40 30 20 10 68 10 20 40 100 VSS = 0 VDD = 5.0 V VDD = 10 V VDD = 15 V 1.0 k 10 k R1, R2, RESISTANCE (OHMS) 100 k 1.0 M B -- Feedback scheme for hysteresis adjustment: POSITIVE COMMON NEGATIVE R1 Figure 3. Typical Threshold Points MC14583B 4 MOTOROLA CMOS LOGIC DATA VDD PULSE GENERATOR 1 PULSE GENERATOR 2 PULSE GENERATOR 3 INPUT = tr = tf = 20 ns Ain DIS Bin Aout Aout Bout Bout VSS CL CL CL CL CL Ain VDD 50% VSS VDD Bin 50% VSS VDD 50% tPLH tf 50% tPHL tr 50% tPHL ton tf toff 90% 10% tr toff ton 90% 10% tf tr 90% 10% VSS VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL 3-STATE DISABLE tPHL Aout tPLH Bout tPLH Aout tPHL Bout tf tr 90% tf NOTE: Dashed lines indicate high output resistance tPHL tPLH 50% 10% tr 50% tPLH tPHL tPLH EXCLUSIVE OR Figure 4. Switching Time Test Circuit and Waveforms MOTOROLA CMOS LOGIC DATA MC14583B 5 VDD VDD Test Switch Position 1 2 2 1 PULSE GENERATOR 1 PULSE GENERATOR 2 1 k* Ain DIS Bin Aout Aout Bout Bout CL 1 SW 2 1 k* ton HL ton LH toff HL toff LH VSS * Metal film, 1%, 1/4 W or greater CL = 15 pF, which includes test circuit capacitance. VDD Ain VSS VDD Bin VSS VDD 50% ton LH Aout 10% VOL ton LH Bout 10% 90% VOH toff LH ton HL VOH 90% toff HL VOH toff LH 90% VOH toff LH 90% VOH VSS VOH 10% (VOH - VOL) VOL VOL VOH 10% (VOH - VOL) VOL VOL 3-STATE DISABLE SWITCH POSITION 2 SWITCH POSITION 1 VOL and VOH refer to the levels present as a result of the 1 k ohm load resistors. Figure 5. 3-State Switching Time Test Circuit and Waveforms MC14583B 6 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 -B- 1 8 C L -T- SEATING PLANE N E F D G 16 PL K M J 16 PL 0.25 (0.010) M M TB S 0.25 (0.010) TA S P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 B 1 8 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M MOTOROLA CMOS LOGIC DATA MC14583B 7 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 9 -B- 1 8 P 8 PL 0.25 (0.010) M B S G F K C -T- SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S DIM A B C D F G J K M P R Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MC14583B 8 *MC14583B/D* MOTOROLA CMOS LOGIC DATA MC14583B/D |
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